The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. The miniaturization of CMOS technology according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. Due to its high integration, heat generated while integrated circuits operate tremendously soars. In order to dissipate heat generated therefrom, packaging methods or structures have been widely proposed to resolve the problem.
FIG. 1 is a cross sectional view showing a prior art package structure for heat dissipation.
The prior art structure comprises a package substrate 100. Solder balls 140 are formed under the package substrate 100. A die 110 is flip-chip mounted to the package substrate 100. Solder balls 107 mechanically and electrically connects the die 110 with the package substrate 100. An under-fill 105 is formed between the die 110 and the package substrate 100. A heat spreader 120 covers the die 110. A thermal interface material, such as a conductive epoxy layer 115, is formed on the die 110. An adhesive layer 125 is applied on the heat spreader 120 so as to adhere the heat sink 130 to the heat spreader 120.
Heat which is generated on the surface of the die 110 due to the operation of integrated circuits is first conductively dispersed across the length and width of the package by the heat spreader 120, using heat conduction, to eliminate hot spots. The heat can be transmitted to the heat sink 130 through the conductive epoxy layer 115, the heat spreader 120 and the adhesive layer 125. The heat sink has a plurality of fins, to provide a large surface area suitable for dissipating heat into the ambient air by convection.
Due to the significant differences of the thermal expansion properties among the package substrate 100, the die 110, the conductive epoxy layer 115, the heat spreader 120, the adhesive layer 125 and the heat sink 130, delamination can occur at the interfaces between the package substrate 100 and the die 110, between the die 110 and the conductive epoxy layer 115, between the conductive epoxy layer 115 and the heat spreader 120, between the heat spreader 120 and the adhesive layer 125 and/or between the adhesive layer 125 and the heat sink 130. Delamination causes the package structure to fail, so as to reduce the packaging yield. For this reason, it is often necessary to include an underfill 105 to relieve the stresses caused by differential thermal expansion during thermal cycling.
U.S. patent application Ser. No. 2004/0070058 A1 discloses an integrated circuit package design. The packaged integrated circuit includes a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.
U.S. patent application Ser. No. 2003/0146520 A1 discloses a flip-chip package with a heat spreader. The package includes a substrate, a chip, a heat spreader, multiple first bumps, multiple second bumps, a first fill material and a second fill material. The substrate has multiple conductive nodes formed on a surface thereof. The chip has an active surface and a corresponding backside surface. The chip further has multiple conductive pads formed on the active surface. The chip is placed over the substrate, and the active surface of the chip faces the surface of the substrate. The heat spreader having a cavity is placed on the substrate, wherein the cavity of the heat spreader faces the substrate and the chip is located inside the cavity. The first bumps are placed between the conductive pads of the chip and the conductive nodes of the substrate. The second bumps are placed between the backside surface of the chip and the heat spreader. The first fill material is filled between the chip and the substrate and covers the first bumps. The second fill material is filled in the cavity of the heat spreader and covers the chip and the second bumps.
Improved heat dissipation methods and structures for die packages are desired.